The present invention relates to a method for fabricating field effect transistor devices.
As gate lengths of MOSFET devices are scaled downward, junction depths for source/drain diffusion must also be decreased to avoid excessive encroachment of source/drain diffusion boundaries under the gate. However, a tradeoff must be made between junction depth and diode sheet resistance--if the junction is too shallow, sheet resistance will be high and device performance (speed) will be limited. Using a low energy arsenic source/drain implant, the practical lower limit for junction depth in optimized short channel MOSFETs is around 150 nm, and the subsequent loss of channel length due to lateral spread of implanted arsenic ions is therefore at least 300 nm for submicron MOSFETS. For a small device even 300 nm represents a significant loss of defined channel length and severely limits device performance.
Several techniques have been used to offset the source/drain implant from the gate and thereby compensate for lateral spread. For example, a sidewall oxide on the polysilicon gate may be used as an offset mask. This technique places stringent demands upon plasma etch uniformity and reproducibility--otherwise unacceptable variations in source/drain junction profiles will be introduced into the process.
Thus it is an object of the present invention to provide a method for fabricating MOSFET transistors with minimal spread of source and drain diffusions underneath the gate.
It is a further object of the present invention to provide a method for fabricating MOSFETs which have minimal overlap between the gate and the source and drain diffusions, without requiring any critically controlled etching steps.
The present invention teaches use of laser-driven diffusion rather than thermally-driven diffusion to drive in the source and drain diffusions. Since the laser illumination is partially screened by the edge of the gate, the temperature profile underneath the gate is highly nonuniform. Since the localized temperature is much higher in the portions of the silicon which are not underneath the gate, diffusion proceeds more rapidly in those surfaces. Thus, the effect of this temperature gradient is that lateral diffusion into the area underneath the gate is retarded with respect to the vertical diffusion which occurs.
A further difficulty with prior art processes for forming source/drain diffusions is the amount of high-temperature history required. For example, in processes using buried contacts, and particularly in advanced CMOS processes using silicided buried contacts and/or both n-type and p-type polysilicon, these complex structures will already be present when the source/drain implants are driven. Reduction of the high-temperature time required at this early stage of the process would make fabrication of buried contacts and multilayer grate-level-interconnect structures much simpler.
A further consideration as VLSI progresses is the increasing sensitivity of the scaled gate oxides. Among the factors in processing which can degrade gate oxides is radiation damage. The radiation induced by ion implantation will typically not be disastrous, but scattered radiation and hot carriers generated by the radiation are capable of inducing empty traps and/or trapped carriers in the gate oxide underneath the polysilicon. The heaviest implant source of gate oxide radiation damage is likely to be the source/drain implant. If this implant could be reduced, damage to gate oxides would also be reduced. Although not presently an urgent problem, any improvement in gate oxide quality is desirable.
The present invention teaches a source/drain drive-in using transient radiant heating. Preferably a highly concentrated surface deposition provides the source of the dopant species, but alternatively an ion implant may be used for the initial dopant introduction, or both implant and surface deposition of different species may be combined.
According to the present invention there is provided:
A method for fabricating a field-effect transistor, comprising the steps of:
providing a semiconductor surface having a first conductivity type; PA0 providing, near said semiconductor surface, a gate electrode defining a channel region within said semiconductor surface beneath said gate electrode, said semiconductor surface also containing source and drain regions separated by said channel region; PA0 introducing a dopant impurity having a second conductivity type at said semiconductor surface in said source and drain regions; PA0 illuminating said source and drain regions with pulsed radiant heating, whereby said second-type impurity is ionized within said semiconductor surface at said source and drain regions.